? semiconductor components industries, llc, 2013 december, 2013 ? rev. 0 1 publication order number: NVDD5894NL/d NVDD5894NL power mosfet 40 v, 10 m , 64 a, dual n ? channel dpak ? 5l features ? low r ds(on) to minimize conduction losses ? high current capability ? avalanche energy specified ? aec ? q101 qualified and ppap capable ? these devices are pb ? free, halogen free/bfr free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 40 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent r jc (notes 1 & 3) steady state t c = 25 c i d 64 a t c = 100 c 45 power dissipation r jc (note 1) t c = 25 c p d 75 w t c = 100 c 38 continuous drain current r ja (notes 1, 2 & 3) steady state t a = 25 c i d 14 a t a = 100 c 10 power dissipation r ja (notes 1 & 2) t a = 25 c p d 3.8 w t a = 100 c 1.9 pulsed drain current t a = 25 c, t p = 10 s i dm 324 a operating junction and storage temperature t j , t stg ? 55 to +175 c source current (body diode) i s 75 a single pulse drain ? to ? source avalanche energy (t j = 25 c, i l(pk) = 25 a, l = 0.3 mh) e as 94 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal resistance maximum ratings parameter symbol value unit junction ? to ? case ? steady state (drain) r jc 2.0 c/w junction ? to ? ambient ? steady state (note 2) r ja 40 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 3. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. dpak 5 ? lead case 175aa marking diagram & pin assignment 40 v 10 m @ 10 v r ds(on) max 64 a i d max v (br)dss 14.5 m @ 4.5 v http://onsemi.com dual n ? channel d s1 g1 s1 g1 g2 drain y = year ww = work week 5894l = specific device code g = pb ? free package yww 58 94lg s2 g2 s2 device package shipping ? ordering information NVDD5894NLt4g dpak ? 5 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. x
NVDD5894NL http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 40 v zero gate voltage drain current i dss v gs = 0 v v ds = 40 v t j = 25 c 1 a t j = 125 c 100 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 50 a 8.3 10 m v gs = 4.5 v, i d = 20 a 11.2 14.5 forward transconductance g fs v ds = 15 v, i d = 10 a 8.8 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1 mhz v ds = 25 v 2103 pf output capacitance c oss 259 reverse transfer capacitance c rss 183 total gate charge q g(tot) v gs = 4.5 v, v ds = 32 v, i d = 20 a 21 nc q g(tot) v gs = 10 v, v ds = 32 v, i d = 20 a 41 threshold gate charge q g(th) v gs = 10 v, v ds = 32 v, i d = 20 a 1.7 nc gate ? to ? source charge q gs 6.9 gate ? to ? drain charge q gd 11.3 plateau voltage v gp 3.5 v switching characteristics turn ? on delay time t d(on) v gs = 10 v, v ds = 32 v i d = 20 a, r g = 2.5 12.4 ns rise time t r 30.2 turn ? off delay time t d(off) 36 fall time t f 54 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v i s = 20 a t j = 25 c 0.88 1.0 v t j = 125 c 0.76 reverse recovery time t rr v gs = 0 v, di s /dt = 100 a/ s i s = 20a 22.8 ns charge time t a 11.2 discharge time t b 11.6 reverse recovery charge q rr 13.7 nc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. pulse test: pulse width 300 s, duty cycle 2%.
NVDD5894NL http://onsemi.com 3 typical characteristics 10 to 5.2 v figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 5 4 3 2 1 0 0 10 30 40 60 80 100 120 6 5 4 3 2 1 0 10 30 50 70 90 100 120 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 9.5 8.5 7.5 6.5 5.5 4.5 3.5 0.008 0.012 0.016 0.020 0.024 0.032 0.036 0.040 100 80 70 60 30 20 10 0 0.005 0.010 0.015 0.020 0.025 0.030 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 150 125 100 75 25 0 ? 25 ? 50 0.50 0.75 1.00 1.25 1.50 1.75 2.00 40 35 30 25 20 15 10 5 100 1000 10,000 100,000 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , normalized drain ? to ? source resistance ( ) i dss , leakage (na) 20 50 70 90 110 v gs = 4.8 v 4.4 v 4.0 v 3.6 v 3.2 v 2.8 v 20 40 60 80 110 v ds = 5 v t j = 150 c t j = ? 55 c t j = 25 c 0.028 i d = 50 a t j = 25 c t j = 25 c v gs = 4.5 v v gs = 10 v 50 40 90 110 v gs = 10 v i d = 50 a 50 175 t j = 150 c t j = 125 c
NVDD5894NL http://onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 40 30 20 10 0 0 500 1000 1500 2000 2500 40 30 25 20 15 10 5 0 0 1 3 4 6 7 9 10 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1000 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 8 10 14 16 20 figure 11. maximum rated forward biased safe operating area figure 12. avalanche characteristics v ds , drain ? to ? source voltage (v) t av , time in avalanche (s) 100 10 1 0.1 0.01 0.1 1 10 100 1e ? 03 1e ? 04 1e ? 05 1e ? 06 1 10 100 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) i peak , drain current (a) c iss v gs = 0 v t j = 25 c f = 1 mhz c oss c rss 2 5 8 45 35 v ds = 32 v t j = 25 c i d = 20 a q t q gs q gd t d(on) t d(off) t r t f 0.9 0.8 6 12 18 v gs = 0 v t j = 25 c t j (initial) = 125 c t j (initial) = 25 c v gs = 10 v t c = 25 c 650 mm 2 2 oz cu pad r ds(on) limit thermal limit package limit 0.01 ms 0.1 ms 1 ms 10 ms dc v gs = 10 v v dd = 32 v i d = 20 a
NVDD5894NL http://onsemi.com 5 typical characteristics figure 13. thermal response pulse time (sec) 10 1 0.001 0.1 0.0001 0.00001 0.01 0.000001 0.01 0.1 1 10 r(t) ( c/w) single pulse duty cycle = 0.5 r jc = 2 c/w steady state 0.2 0.1 0.05 0.02 0.01
NVDD5894NL http://onsemi.com 6 package dimensions dpak ? 5, center lead crop case 175aa issue a d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 5 ? lead dpak central lead crop scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NVDD5894NL/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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